通过同步驱动,在超声量子比特中使用原生多量子比特网关.
Sagar Silva Pratapsi1,2, Diogo Cruz3,4, Paulo André3,4
1Instituto Superior Técnico, Universidade de Lisboa, Lisbon, Portugal. spratapsi@tecnico.ulisboa.pt.
Scientific reports
|October 30, 2024
概括
并行预校准的量子脉冲优化量子门,显著减少错误和门时间,以改善量子计算. 这一策略提高了各种量子门和应用的可靠性.
科学领域:
- 量子计算是一种量子计算.
- 量子信息科学 量子信息科学
- 量子硬件优化 量子硬件优化
背景情况:
- 量子计算有望解决难以解决的问题,但受到短连贯时间和不完美的电路硬件映射的限制.
- 由于硬件限制,当前的量子设备在实现高保真性和效率方面面临着挑战.
研究的目的:
- 为预校准脉冲提供硬件级并行化策略,以优化量子门.
- 用这种并行化技术来证明量子门的可靠性提高和门时间缩短.
主要方法:
- 实施量子门预校准脉冲的硬件级并行化.
- 使用循环基准测试和过程断层扫描来测量网关错误和保真度.
- 专注于 门,并扩展到 CNOT 和 CZ 门.
主要成果:
- 与串行连接相比,大门错误减少了一半.
- 证明了对门的改进忠实性和减少门时间.
- 验证了并行化策略对其他基本量子门的适用性.
结论:
- 硬件级脉冲并行化是优化量子门的有效且易于实施的策略.
- 这种方法在保真度和网关速度方面提供了实质性的改进,这对于推动量子计算至关重要.
- 该策略显示了对关键量子任务 (如哈密尔顿模拟,振幅放大和错误纠正) 的潜在好处.
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