用于概率计算的CMOS单光子雪崩二极管电路
William Whitehead1, Wonsik Oh1, Luke Theogarajan1
1Department of Electrical and Computer Engineering, UCSB, Santa Barbara, CA 93106 USA.
概括
可变速率SPAD电路 (VRSC) 为概率计算提供了一个新的硬件随机数源. 优化的设计展示了高效的,低可变性的概率位 (P-bit),适合CMOS集成.
科学领域:
- 集成电路设计 集成电路设计
- 量子计算硬件 量子计算硬件
- 固态物理 固态物理
背景情况:
- 本质上随机的硬件设备对于概率计算至关重要.
- 单光子雪崩二极管 (SPAD) 和变速SPAD电路 (VRSC) 是一个有前途的硬件随机数生成器.
- 之前的工作为采样和回火Ising和Potts模型建立了VRSC.
研究的目的:
- 为推进对VRSC设计用于概率计算的理解.
- 探索SPAD和VRSC处理电路的设计权衡.
- 在65纳米CMOS过程中评估VRSC性能.
主要方法:
- 在65纳米CMOS工艺中制造和表征多个VRSC设计.
- 评估了三种SPAD设计和三种处理电路类型.
- 分析包括面积,速度,可变性和转移函数在内的指标.
主要成果:
- 小型SPAD适用于概率计算,高暗数率是可以接受的.
- 用于概率计算的SPAD可以很容易地集成到标准的CMOS过程中.
- 新的基于时间到模拟的设计提供了分析转移功能,而基于过器的设计在较小的足迹中提供了较低的变化.
- 制造的概率位 (P-bit) 实现50MHz的位翻转率和可控制的模拟回火温度.
结论:
- VRSC的设计选择显著影响了性能指标,如面积,速度和可变性.
- 优化的VRSC为概率计算应用提供了可行的硬件解决方案.
- 该研究为CMOS技术中的硬件随机数生成器的设计和集成提供了宝贵的见解.
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