解决互连挑战以提高计算性能
Joon-Seok Kim1, Joonyun Kim1, Dae-Jin Yang1
1Device Research Center, Samsung Advanced Institute of Technology, Suwon, Korea.
概括
由于相互连接电阻-电容 (RC) 延迟,半导体设备的缩放面临限制. 这项研究提出了材料和设备战略,以克服这一瓶,以提高性能.
科学领域:
- 电气工程
- 材料科学
- 半导体物理
背景情况:
- 现代半导体技术将许多设备集成到一个芯片上,仅限于扩展性能.
- 相互连接对于连接晶体管至关重要,在缩小尺寸时表现出增强的电阻,导致显著的电阻-电容 (RC) 延迟.
- 这种RC延迟越来越多地控制了信号处理时间,而不是晶体管切换速度.
研究的目的:
- 解决先进半导体设备中相互连接RC延迟造成的性能瓶.
- 探索和提出减轻互连电阻和电容性的新策略.
- 研究提高信号处理速度的材料和设备级解决方案.
主要方法:
- 对互连缩放对电阻的影响分析.
- 审查当前的替代互连材料研究.
- 探索创新的设备架构以减少RC延迟.
- 纳米级互连中电阻和电容的理论建模.
主要成果:
- 识别了连接电阻的指数增长与尺寸的减少作为主要的性能限制.
- 突出了当前集成电路中RC延迟对晶体管开关延迟的优势.
- 确定需要替代材料和设备结构来克服相互连接的局限性.
结论:
- 单纯的设备扩展不足以改善集成电路的未来性能.
- 材料创新和新型设备设计对于克服互连RC延迟至关重要.
- 拟议的战略为提高先进半导体技术的信号处理速度提供了途径.
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