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一个新型的节能4位维达式乘法器,使用修改后的GDI方法在32nm技术

K Nishanth Rao¹, D Sudha², Osamah Ibrahim Khalaf³

¹Department of ECE, MLR Institute of Technology, Hyderabad, India.

|December 13, 2024

概括

这项研究比较了使用Gate Diffusion Input (GDI),CMOS和Transmission Gate (TG) 技术的4位Vedic乘法器. 在延迟,面积和功耗方面,GDI技术表现出卓越的性能.

科学领域:

数字电路设计数字电路设计
这是一种VLSI技术.
计算机算术计算机算术

背景情况:

乘数对于集成电路来说至关重要,它会影响效率和性能.
维达式乘法器提供了基于古代印度数学的固有速度和效率.
优化乘数设计是高级计算任务的关键.

研究的目的:

使用GDI,CMOS和TG技术分析和比较4位Vedic乘法器设计.
为了评估不同添加器架构 (RCA,CLA,CSA) 的性能,面积和功耗.
确定最有效的技术和添加组合,以实现高效的乘数实现.

主要方法:

在GDI,CMOS和TG技术中设计和优化4位Vedic乘法器.
集成各种添加器架构:波携带添加器 (RCA),携带视角添加器 (CLA) 和携带跳过添加器 (CSA).
通过Tanner EDA.在32nm技术中使用晶体管计数,延迟,功耗和功耗延迟产物 (PDP) 等参数来评估设计.

主要成果:

门扩散输入 (GDI) 技术显示出相对于CMOS和TG的显著优势.
基于GDI的Vedic乘法器表现出更低的延迟,更小的面积和更低的功耗.
该研究量化了电源延迟产品 (PDP) 的改进,有利于GDI实施.

结论:

GDI技术为设计高效的4位Vedic乘法器提供了一种高度有效的方法.
技术的选择和添加器架构显著影响电路性能指标.
这项研究为优化数字信号处理和算术电路设计提供了宝贵的见解.

关键词:

区域区域区域区域区域区域区域区域区域区域区域这是一个CMOS系统.卡里跳蛇 (英语:Caary skip adder) 是一种跳蛇.携带看向前的毒蛇延迟延迟延迟的时间门的扩散输入输入.在PDP中,PDP是PDP.波动携带添加器 (Ripple carry adder) 是一个波动携带添加器.传输门的传输门.

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