一种基于强化学习的方法,用于在多FPGA平台上的高效路由
Umer Farooq1, Habib Mehrez2, Najam Ul Hasan3
1School of Computer Science and Engineering, University of Sunderland, Sunderland SR6 0DD, UK.
Sensors (Basel, Switzerland)
|January 11, 2025
概括
本研究引入了强化学习 (RL) 框架,以加速多FPGA原型设计中的FPGA间路由. RL方法显著减少了路由时间,从而导致更快的整体设计后端流.
科学领域:
- 计算机工程 计算机工程
- 硬件加速器 硬件加速器
- 人工智能的人工智能
背景情况:
- 多FPGA原型设计可实现现实世界的测试和循环精确的设计验证.
- 跨FPGA路由是多FPGA原型设计中的一个关键和耗时的步骤.
- 跨FPGA路由的复杂性随着现代硬件设计而增加.
研究的目的:
- 开发和评估基于强化学习 (RL) 的框架,以加快FPGA之间的路由过程.
- 在不影响结果质量 (QoR) 的情况下,优化RL框架的勘探-开发权衡 (ε-贪的方法).
主要方法:
- 整合基于RL的框架,用于FPGA之间的路由.
- 在RL框架内实施一个e-greedy战略.
- 通过使用14个复杂的基准,对已建立的可路由性驱动和时间驱动的路由方法进行比较分析.
主要成果:
- 与路由能力驱动的方法相比,拟议的RL框架在FPGA间路由中实现了平均45%的加快速度.
- 与时间驱动的路由方法相比,RL框架平均提供了32%的加快速度.
- 总体后端流速加快的22%和15%被观察到与路由性和时间驱动的方法,分别.
结论:
- 基于RL的框架有效地加速了多FPGA原型设计中的FPGA间路由.
- 这种加速有助于显著提高硬件设计后端流程的整体速度.
- 拟议的方法为复杂的原型设计挑战提供了一个有希望的解决方案.
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