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稀疏转换FPGA加速器基于多银行哈希选择
Jia Xu1,2,3, Han Pu1,2, Dong Wang1,2
1Institute of Information Science, Beijing Jiaotong University, Beijing 100044, China.
Micromachines
|January 25, 2025
概括
本研究介绍了稀疏神经网络的新型硬件加速技术,显著提高能源效率和减少延迟. 优化的加速器在FPGA上实现了高吞吐量与低功耗.
科学领域:
- 计算机工程 计算机工程
- 人工智能的人工智能
- 硬件加速器 硬件加速器
背景情况:
- 深度卷积神经网络 (DCNN) 加速对人工智能至关重要,但通用设备对稀疏模型缺乏效率.
- 现有的神经网络加速器在最佳效率,低延迟和最小功耗方面面临着挑战.
- 稀疏神经网络加速是一个活跃的研究领域,有可能进一步优化.
研究的目的:
- 研究和提出三种关键技术,用于稀疏神经网络的硬件加速.
- 通过设计专门的电路来提高能源效率,从而消除在稀疏内核中对零值的计算.
- 为了提高离芯片内存访问效率,并减少卷积神经网络加速器中的延迟.
主要方法:
- 开发了一个专门的计算电路来检测和跳过零值计算在稀疏的卷积内核.
- 使用Vitis HLS编译器优化插件来增强对数据访问模式的芯片上带宽利用率.
- 提出了一个共享功能地图缓存与基于哈希的索引算法,以实现高效的异步卷积,减少芯片内存的使用.
主要成果:
- 专用电路通过消除零值计算来提高能源效率.
- 编译器优化提高了离芯片内存访问效率和数据处理.
- 共享缓存设计使有效的异步卷积成为可能,节省了芯片上的资源.
- 根据ResNet50对Intel Arria 10 1150GXFPGA的推断,在22W的功耗下实现了497个GOPS的吞吐量 (相当于1579个GOPS).
结论:
- 提出的技术显著提高了稀疏神经网络加速器的效率,延迟和功耗.
- 优化的加速器在DCNN推断任务中表现出高性能和高能效.
- 这项工作为部署高效的神经网络硬件加速提供了可行的解决方案.
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