用于二维低开销量子计算的LDPC-cat代码
Diego Ruiz1,2, Jérémie Guillaud3, Anthony Leverrier4
1Alice & Bob, 49 Bd du Général Martial Valin, 75015, Paris, France. diego.ruiz@alice-bob.com.
Nature communications
|January 25, 2025
概括
这项研究引入了一种新的量子计算架构,结合了低密度平价检查 (LDPC) 代码和猫量子比特. 这种方法显著减少了实施逻辑量子比特的开销,实现了可扩展量子计算的高错误抑制.
科学领域:
- 量子计算是一种量子计算.
- 量子错误纠正方法 量子错误纠正方法
- 量子信息科学 量子信息科学
背景情况:
- 物理量子位错误是大规模量子计算的一个主要障碍.
- 目前的错误纠正方法需要大量的物理量子比特,增加开销.
- 现有的策略,如低密度平价检查 (LDPC) 代码和猫量子比特提供部分解决方案.
研究的目的:
- 开发一个高效的量子计算架构,显著减少量子比特开销.
- 将LDPC代码和猫量子比特结合起来,以实现协同式错误抑制.
- 在一个紧的758量子比特芯片上实现100个逻辑量子比特.
主要方法:
- 低密度平价检查 (LDPC) 代码与猫量子比特的集成.
- 设计一个具有短距离交互和轻重稳定器的2D硬件架构.
- 使用额外一层路由猫量子位实现容错的通用逻辑门.
主要成果:
- 实现了用于量子错误校正的极低开销架构.
- 在758量子比特芯片上展示了100个逻辑量子比特的实现,物理错误率为~0.1%.
- 每个逻辑量子位 (εL) 的每周期总逻辑错误概率低于10-8.
- 保持了局部连接和逻辑门的高并行能力.
结论:
- 拟议的架构通过最大限度地减少量子比特开销,为可扩展的量子计算提供了可行的途径.
- 该设计与现有的硬件限制兼容,类似于表面代码.
- 该架构支持逻辑门的高效实现,增强实用的量子计算.
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