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通过表轴单体立体3D集成,通过低功耗的2D门全方位逻辑实现3D集成
Junchuan Tang1, Jianfeng Jiang2, Xiaoyin Gao1
1Center for Nanochemistry, Beijing Science and Engineering Center for Nanocarbons, Beijing National Laboratory for Molecular Sciences, College of Chemistry and Molecular Engineering, Peking University, Beijing, China.
Nature materials
|February 14, 2025
概括
研究人员开发了一个晶圆尺度的二维半导体通道全方位 (GAA) 晶体管. 这一创新使未来的电子设备能够实现超越的性能和能源效率提升.
科学领域:
- 材料科学与工程 材料科学与工程
- 纳米技术 纳米技术
- 半导体物理 半导体物理
背景情况:
- 晶体管小型化对于提高设备性能,能源效率和集成密度至关重要.
- 二维 (2D) 半导体在安格斯特罗姆节点提供了门周围 (GAA) 场效应晶体管 (FET) 的潜力,为功率扩展提供了优越的门控制.
- 2D GAA异构结构与原子光滑接口的可扩展整合仍然是一个重大挑战.
研究的目的:
- 开发一个晶圆尺度,单立体3D集成的2D GAA异构结构.
- 为了实现2D半导体和高-κ介电体之间的原子光滑接口,以提高晶体管性能.
- 为了证明2D GAA FETs在超越电子领域的潜力.
主要方法:
- 低温单体三维整合. 低温单体三维整合.
- 高流动性二维半导体Bi2O2Se与高-κ层原生氧化物介电体Bi2SeO5的表轴集成.
- 制造尺寸缩放的2D GAA FET,其门长度为30 nm.
主要成果:
- 实现了晶圆尺度,多层堆叠,单晶的2D GAA配置,具有原子光滑的接口.
- 证明了280cm2V-1s-1的高电子流动性和62mV dec-1的近乎理想的下值摆动.
- 展示了超低的操作电压 (0.5V),高的状态电流 (>1 mA μm-1),超低的内在延迟 (1.9 ps) 和出色的能量延迟产物 (1.84 × 10-27 Js μm-1).
结论:
- 开发的晶圆尺度2D GAA系统提供了显著的性能和功率优势.
- 这种方法克服了高级晶体管架构中2D材料的关键集成挑战.
- 这项技术对未来超越的单立体3D集成电路具有很大的潜力.
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