低值薄膜晶体管的读取电压依赖的突触特征,具有hf化ZnO活性层
Jeongseok Pi1, Danyoung Cha1, Sungsik Lee2
1The Department of Electronics Engineering, Pusan National University, Busan, 46241, Republic of Korea.
Scientific reports
|April 17, 2025
概括
这项研究量化了读取电压如何影响Hf-ZnO突触晶体管. 更高的读取电压通过抑制电子回收来改善保留时间,证明偏差应力可以提高设备的稳定性.
科学领域:
- 材料科学 材料科学 材料科学
- 固态电子 固态电子
- 神经形态工程的神经形态工程
背景情况:
- 突触薄膜晶体管 (Syn-TFT) 对于神经形态计算至关重要.
- 了解操作参数的影响,如读取电压,对于设备优化至关重要.
- 氧化 (Hf-ZnO) 为Syn-TFT提供了有前途的材料特性.
研究的目的:
- 量化分析Hf-ZnO Syn-TFTs的突触特征.
- 为了研究读取电压 (Vread) 对设备性能的影响,包括编程速度和保留.
- 探索值电压 (VT) 转移和电子捕获在设备行为中的作用.
主要方法:
- 使用了一个低于值的操作Hf-ZnO Syn-TFT.
- 在不同的读取电压下 (2.3V和0.6V) 进行了突触特征的定量分析.
- 应用正负编程脉冲来诱导值电压转移,并监控输出电流和保留特征.
主要成果:
- 在值电压 (VT) 附近的高Vread (2.3V) 压低了输出电流,这是由于从电子陷中获得的正VT转移造成的.
- 在平带电压 (VFB) 附近的下Vread (0.6V) 通过从电子脱落中通过负VT转移促进了输出电流.
- 在较低的Vread,由于的下值斜率,编程速度更快,而在较高的Vread,保留时间明显更长.
- 在较高的Vread中,正偏差应力抑制了电子回收,增加了保留时间.
结论:
- 读取电压显著影响Hf-ZnO Syn-TFT的突触特性,影响编程速度和保留.
- 蓄意应用偏向应力,特别是在较高的读取电压下,可用于改善设备保留时间.
- 这些发现为优化Syn-TFTs提供了对稳定和高效的神经形态应用的洞察力.
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