通过深度学习和动态部分重新配置来缓解FPGA的侧通道攻击
Sesibhushana Rao Bommana1, Sreehari Veeramachaneni2, Syed Ershad3
1Department of Electrical & Electronics Engineering, BITS Pilani Hyderabad Campus, Hyderabad, 500078, India. p20200107@hyderabad.bits-pilani.ac.in.
Scientific reports
|April 21, 2025
概括
本研究提出了一种使用深度学习 (DL) 和在现场可编程门数组 (FPGA) 上动态部分重配置 (DPR) 的新框架,以对抗侧通道攻击 (SCAs). 这种自适应的方法可以动态地重新配置硬件,增强针对低延迟的不断变化的威胁的安全性.
科学领域:
- 计算机工程 计算机工程
- 网络安全 网络安全
- 人工智能的人工智能
背景情况:
- 传统的静态防御对自适应侧通道攻击 (SCAs) 不够.
- 现场可编程门阵列 (FPGA) 由于其可重新配置的性质,容易受到SCA的攻击.
- 动态适应对于有效的实时硬件安全至关重要.
研究的目的:
- 为FPGA安全引入一个结合深度学习 (DL) 和动态部分重配置 (DPR) 的框架.
- 为了证明在运营中的FPGAs中适应性减轻功率侧通道攻击.
- 建立一个积极的防御机制,以对抗不断发展的硬件威胁.
主要方法:
- 整合DL模型用于威胁分析和DPR用于实时硬件重新配置.
- 动态重新配置FPGA资源以破坏SCA模式.
- 专注于减轻电源侧通道攻击,并有可能扩展到其他SCA类型.
主要成果:
- 在20个时钟周期内实现了SCA的实时检测和缓解.
- 通过适应性对策,证明了对电力侧通道攻击的弹性.
- 展示了框架在现实FPGA设计上有效运行的能力.
结论:
- 该DL-DPR框架提供了一个转向主动硬件安全的范式转变.
- 结合AI和FPGA技术,重新定义了硬件系统的自适应性安全机制.
- 拟议的方法大大提高了FPGA设计的弹性,并为未来的自适应性安全研究铺平了道路.
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