ADPO:适应式DRAM控制器用于性能优化
Zhuorui Liu1, Yan Li2, Xiaoyang Zeng2
1School of the Academy for Engineering and Technology, Fudan University, Shanghai 200433, China.
Micromachines
|April 26, 2025
概括
本研究介绍了双数据速率SDRAM (DDR) 的自适应调度架构,以减少内存子系统中的延迟. 新型控制器优化了对像深度神经网络这样的苛刻应用程序的性能,显示了显著的延迟改进.
科学领域:
- 计算机工程 计算机工程
- 记忆系统的架构 记忆系统的架构
- 高性能计算 高性能计算
背景情况:
- 像深度神经网络这样的新兴应用程序需要高离芯片内存带宽和低延迟的双数据速率SDRAM (DDR).
- 芯片包和系统板上的物理限制使得DDR带宽的增加和延迟的降低成本过高.
- 现有的DDR子系统在满足高级计算任务的严格延迟要求方面面临挑战.
研究的目的:
- 介绍一个新的DDR子系统架构,以优化延迟.
- 通过对用例敏感的自适应调度控制器来解决延迟问题.
- 为了提高内存密集型应用程序的系统性能.
主要方法:
- 在DDR调度中重新评估传统的脱机制和准静态仲裁.
- 实现一个等级级的定时感知读/写转换仲裁器.
- 根据观察到的工作负载模式,动态调整读写队列值和周转设置.
主要成果:
- 拟议的自适应调度算法在各种现实场景中展示了显著的优势.
- 实验表明,在各种工作负载和配置中,延迟减少的幅度从10%到50%.
- 该架构有效地优化了DDR子系统性能,并提高了整体系统性能.
结论:
- 新的自适应调度架构成功地减少了DDR延迟.
- 使用案例敏感控制器提高了对要求高的应用程序的内存子系统性能.
- 这种方法为克服高带宽,低延迟内存系统的物理限制提供了可行的解决方案.
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