基质铜痕迹的概述 通过实验,表征和数值模拟破裂
Wei Yu1, Faxing Che1, Vance Liu2
1Micron Semiconductor Asia Operations Pte. Ltd., 990, Bendemeer Road, Singapore 339942, Singapore.
Micromachines
|April 26, 2025
概括
这项研究分析了内存包中的铜痕迹裂,识别了故障模式和传播路径. 增强接电阻 (SR) 通过减少温度循环测试 (TCT) 期间的应力和应变,显著提高了可靠性.
科学领域:
- 材料科学 材料科学 材料科学
- 机械工程 机械工程
- 半导体包装 半导体包装
背景情况:
- 存储器包中的高输入/输出需求需要精确的跟踪尺寸,挑战当前的设计.
- 在温度循环测试 (TCT) 期间,基质铜痕迹裂是一个关键的可靠性问题.
研究的目的:
- 分析内存包中的铜痕迹裂机制.
- 识别常见的故障模式,启动地点和传播路径.
- 评估材料性能和设计参数对可靠性的影响.
主要方法:
- 实验观测和材料表征 (包括纳米沉积和应力应变测试).
- 使用有限元素 (FE) 模型进行数值模拟.
- 实验设计 (DOE) 用于评估接电阻 (SR) 的性能.
主要成果:
- 铜中较高的E/H值与较低的故障率相关.
- FE模拟准确地预测了痕迹裂的位置.
- 痕迹宽度和材料性能的变化显示了塑料应变的显著差异 (高达40%和30%).
- 高强度SR降低了高达75%的压力和应变.
结论:
- 接电阻 (SR) 在铜痕迹可靠性中起着至关重要的作用.
- SR故障显著增加了塑料应变积累,突出了对强大的SR材料和设计的需求.
- 了解裂纹机制和材料特性是提高内存包可靠性的关键.
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