泰勒系列基于插曲的直接数字频率合成器,具有高内存压缩比
Kalle I Palomäki1, Jari Nurmi1
1Wireless Research Center, Tampere University, 33720 Tampere, Finland.
Sensors (Basel, Switzerland)
|April 26, 2025
概括
这项研究介绍了一种新的16位方格直接数字频率合成器 (DDFS),使用泰勒序列插曲实现高内存压缩 (5178:1) 和优异的信号纯度 (-102.9 dBc SFDR).
科学领域:
- 数字信号处理 数字信号处理
- 集成电路设计 集成电路设计
背景情况:
- 直接数字频率合成器 (DDFS) 在平衡内存压缩与输出信号纯度方面面临着挑战.
- 有效的相变幅转换对于DDFS性能至关重要.
研究的目的:
- 呈现一个16位方格DDFS设计,增强内存压缩和信号纯度.
- 为了证明二次泰勒数列多项式插值在DDFS中的相变幅转换的有效性.
主要方法:
- 用了二次泰勒数列多项式插值来进行相变幅转换.
- 实现了通过Python模型优化的细分查找表 (LUT) 方法.
- 使用寄存器传输级VHDL设计和合成了DDFS,并在AMD Artix 7 FPGA上实现.
主要成果:
- 实现了 5178:1 的内存压缩比.
- 产生高光谱纯度的正弦和正弦输出,达到-102.9dBc的无伪动态范围 (SFDR).
- 需要的最小FPGA资源:107个逻辑切片和3个DSP切片.
结论:
- 拟议的DDFS设计有效地克服了内存压缩和信号纯度之间的权衡.
- 第二阶泰勒序列插值为高性能DDFS提供了一种资源高效的方法.
- 该设计通过FPGA实施并具有竞争力的资源利用来证明其实际可行性.
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