设计,合成和模拟使用MOS晶体管作为分布式电阻电容装置的小数序元件
David Kubanek1, Aleksandr Shadrin2, Pavel Seda2
1Faculty of Electrical Engineering and Communication, Brno University of Technology, Technicka 3082/12, 616 00, Brno, Czechia. kubanek@vut.cz.
Scientific reports
|April 27, 2025
概括
本研究引入了一种新的方法,用于设计使用标准金属氧化物半导体 (MOS) 晶体管的小数序元素 (FOE). 开发的技术可以为先进的电路应用创建精确的电子元件,具有分数级阻抗.
科学领域:
- 电气工程 电气工程
- 材料科学 材料科学 材料科学
- 计算机工程 计算机工程
背景情况:
- 分数顺序元素 (FOE) 提供了独特的阻抗特性,这些特性在传统的整数顺序组件中是无法实现的.
- 使用标准集成电路技术实现FOE一直是一个重大挑战.
- 现有的合成FOE的方法通常是复杂的,并且与当前的制造工艺不容易兼容.
研究的目的:
- 提出一种新的合成方法,用于设计使用金属氧化物半导体 (MOS) 晶体管的小数序元素 (FOE).
- 为了使FOE的制造使用现有的集成电路制造技术.
- 通过模拟来验证拟议的设计方法.
主要方法:
- 模拟MOS晶体管作为均分布的电阻电容层结构.
- 使用遗传算法优化MOS晶体管互连和尺寸,以满足所需的FOE特性.
- 开发了一个图形用户界面 (GUI),以方便合成过程.
- 该设计使用TSMC 65nm技术的Cadence后布局模拟进行了验证.
主要成果:
- 成功合成了具有从5到85度的入口阶段的FOEs.
- 布局后的模拟证实了设计的准确性,显示大小和相位误差分别低于0.5%和0.1度.
- 合成的FOE的验证频率范围为1kHz至10MHz.
结论:
- 拟议的合成方法有效地使用MOS晶体管设计分数顺序元素 (FOE).
- 该方法与当前的集成电路制造技术兼容,为实际的FOE制造铺平了道路.
- 经过验证的模拟结果显示了高精度和适合未来的真实应用的适用性.
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