低延迟的FPGA实现了扭曲的爱德华曲线加密技术硬件加速器在质量场上的硬件加速器
Md Rownak Hossain1, Md Sazedur Rahman2, Kh Shahriya Zaman3
1Electrical and Electronic Engineering, Khulna University of Engineering & Technology, Khulna, 9203, Bangladesh.
Scientific reports
|April 29, 2025
概括
本研究介绍了一种高效的硬件架构,用于点乘法 (PM) 在圆曲线密码学使用FPGA. 这种新的设计实现了高吞吐量和低延迟,这对于安全,高速的无线通信至关重要.
科学领域:
- 计算机工程 计算机工程
- 密码学 密码学 密码学 密码学
- 硬件加速器 硬件加速器
背景情况:
- 圆曲线加密 (ECC) 的性能严重依赖于高效的点乘法 (PM) 架构.
- 现有的ECC硬件加速器在优化PM操作的速度和安全性方面面临着挑战.
研究的目的:
- 在Edwards25519曲线上设计和实施一个高效的ECC点乘法 (PM) 硬件加速器.
- 开发一个统一的点操作模块,以提高加密硬件的性能和安全性.
主要方法:
- 在现场可编程门阵列 (FPGA) 上硬件实现模块化算术,组运算和PM.
- 在投射坐标中开发一个统一的点操作模块,用于组合点加和加倍.
- 在256位素字段上利用Edwards25519曲线.
主要成果:
- 统一点操作模块在646个时钟周期内完成操作,提供更好的安全性.
- 拟议的点乘法 (PM) 模块在Xilinx Virtex-5 FPGA上在117.8 MHz实现1.4毫秒的延迟.
- 对于256位密钥,记录了183.38 kbps的吞吐量,证明了竞争力的性能.
结论:
- 开发的基于FPGA的PM架构提供了高吞吐量和低延迟.
- 这种架构适用于高速无线通信网络中的快速数据加密.
- 统一的模块设计提高了ECC硬件加速的效率和安全性.
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