在Artix-7 FPGA上的异质点击延迟线时间到数字转换器
Riguang Chen1,2, Ping Chen1,3, Kuinian Li1
1Key Laboratory of Ultra-Fast Photoelectric Diagnostics Technology, Xi'an Institute of Optics and Precision Mechanics of CAS, Xi'an 710119, China.
本研究介绍了一种新的3点触摸异质触摸延迟线 (TDL) 架构,用于基于FPGA的时间到数字转换器 (TDC). 新设计实现了高精度的多通道飞行时间测量.
科学领域:
- 数字电子产品数字电子产品
- 嵌入式系统工程 嵌入式系统工程
- 科学仪器仪表科学仪器仪表
背景情况:
- 现场可编程门阵列 (FPGA) 为时间到数字转换器 (TDC) 提供了具有成本效益,高精度和快速开发的解决方案.
- 在高能物理,自动驾驶和医疗成像等科学学科中,TDC对于精确的定时测量至关重要.
研究的目的:
- 为基于FPGA的TDCs提供一种新的3点触摸异质触摸延迟线 (TDL) 架构.
- 为了增强多道飞行时间测量能力.
- 与现有的FPGA TDC设计相比,实现更高的时间分辨率和精度.
主要方法:
- 在Xilinx Artix-7 FPGA上实现一个3键异质的TDL架构,基于开源的jTDC.
- 使用双循环编码和校准方法与jTDC的动态缓存机制相结合.
- 针对飞行时间测量的提议TDC架构的实验评估.
主要成果:
- 一个最佳的3点点异质TDL架构实现了23,220 psi的分辨率和17,520 ps的精度.
- 一个最佳的4点点异质TDL架构显示了17530 ps的分辨率和17213 ps的精度.
- 实施的TDC展示了单循环死亡时间和多道扩展能力.
结论:
- 拟议的3点点异质TDL架构为FPGA-based TDCs提供了显著的分辨率和精度改进.
- 这种架构适用于苛刻的多通道飞行时间应用程序.
- 该研究提供了与最先进的FPGA TDC进行有价值的比较.
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