一个阶段间隔 FinFET 设计用于 FPGA 应用中的增强设备性能
Meysam Zareiee1, Mahsa Mehrad2, Abdulkarim Tawfik2
1Department of Design, Manufacturing and Engineering Management, University of Strathclyde, Glasgow G1 1XQ, UK.
Micromachines
|August 28, 2025
概括
一种新型的阶段间隔结构FinFET (S3-FinFET) 改进了静电控制,并减少了晶体管中的泄漏电流. 这种设计非常适合先进的可编程门阵列 (FPGA),提高功率效率和速度.
科学领域:
- 半导体设备物理
- 先进的晶体管架构
- 纳米电子
背景情况:
- 由于短通道效应和门泄漏,传统的MOSFET在10nm以下的尺度上面临限制.
- FinFET,特别是SOI的无连接变体,为缩放节点提供了增强的静电控制.
- 需要改进晶体管设计以满足现代集成电路的需求.
研究的目的:
- 提出和评估一个新的阶段间隔结构FinFET (S3-FinFET).
- 通过先进的模拟技术研究S3-FinFET的性能增强.
- 评估S3-FinFET适用于诸如现场可编程门阵列 (FPGA) 这样的应用.
主要方法:
- 使用三层HfO2/Si3N4/HfO2间隔器开发新的S3-FinFET架构.
- 使用2D技术计算机辅助设计 (TCAD) 模拟进行设备评估.
- 分析关键性能指标,包括传输/输出特征,开启/关闭比率,下值波动 (SS) 和排水诱导的屏障降低 (DIBL).
主要成果:
- S3-FinFET显著改善了静电控制和减少了寄生效应.
- 关键性能指标显示泄漏电流抑制和高频运行显著改善.
- 与传统设计相比,模拟显示出更高的下值 (SS) 和排水诱导的障碍降低 (DIBL).
结论:
- S3-FinFET架构为克服深度扩展晶体管的局限性提供了一个有希望的解决方案.
- 拟议的设计表现出对节能和高速电子应用至关重要的增强性能特征.
- 由于其提高的速度和信号完整性,S3-FinFET特别适合于现场可编程门阵列 (FPGA).
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