优化散装线性 MOS 伪电阻的设计策略
Lorenzo Benatti1, Tommaso Zanotti1, Francesco Maria Puglisi1
1Dipartimento di Ingegneria "Enzo Ferrari", Università di Modena e Reggio Emilia, Via P. Vivarelli 10/1, 41125 Modena, MO, Italy.
Micromachines
|August 28, 2025
概括
本研究介绍了金属氧化物半导体场效应晶体管 (MOSFET) 伪电阻的优化偏移电路,通过减少面积,偏移和功耗来改进集成电路设计.
科学领域:
- 集成电路设计
- 半导体设备物理
背景情况:
- 大量线性化技术扩展了伪电阻元件的MOSFET线性区域.
- 现有的方法可能很复杂,影响面积,偏移和功耗.
研究的目的:
- 为 MOSFET 伪电阻提供一种新的,简化的偏移电路.
- 在不增加设计复杂性的情况下优化面积,偏移和功耗.
主要方法:
- 专注于优化复合MOSFET结构的门偏移电路.
- 使用布局后的模拟来验证设计策略.
- 应用该策略来设计用于神经信号采集的带通波器.
主要成果:
- 拟议的偏移电路优化了区域,偏移和功耗.
- 模拟证实了设计策略的有效性.
- 波扭曲和噪声分析验证了该方法的实际应用.
结论:
- 新的偏移电路设计有效地提高了MOSFET伪电阻的性能.
- 这种方法为紧和高效的集成电路设计提供了实用解决方案.
- 该策略已被验证用于诸如神经信号采集过器之类的应用.
相关概念视频
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