测试模式优化方案基于混合殖民地优化
1Department of Electronics and Communication Engineering, Anna University, Chennai, 600025, India. ponasha13@gmail.com.
Scientific reports
|October 2, 2025
概括
本研究介绍了一种混合群优化技术,用于减少连续电路测试中的功耗. 与现有方法相比,该方法显著减少了过渡数量,并降低了功耗.
科学领域:
- 电气工程 电气工程
- 计算机科学 计算机科学
- 在 VLSI 设计中,
背景情况:
- 设备的小型化增加了数字电路测试的复杂性.
- 在测试期间,高开关活动会导致功耗增加.
- 尽量减少测试模式之间的转换是减少测试功率的关键.
研究的目的:
- 提出一种混合群优化 (HACO) 技术,以减少连续电路测试中的功耗.
- 通过减少它们的数量和重新排序它们以降低切换活动来优化测试模式.
主要方法:
- 整合群优化 (ACO) 与Kullback-Leibler (KL) 差异,以减少测试模式.
- 采用Prim的算法来重新排序测试模式以尽量减少过渡.
- 使用ISCAS'89基准电路进行实验评估.
主要成果:
- 与传统的ACO相比,实现了71.60%的过渡数量减少.
- 与线性反转移注册 (LFSR) 生成的模式相比,实现了平均功率减少57.48%.
- 在低功率VLSI测试中表现出显著的有效性.
结论:
- 拟议的HACO技术有效地减少了连续电路测试期间的功耗.
- 这种方法为优化现代数字电路中的测试模式提供了一个有希望的方法.
- 在VLSI测试中,HACO在过渡数和功率降低方面取得了显著的改进.
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