使用碳纳米管晶体管在四元逻辑中设计和优化四元乘法器
Sobhan Aghamalizadeh Toosanloo1, Javad Javidan2
1University of Mohaghegh Ardabili, Ardabil, Iran.
Scientific reports
|October 14, 2025
概括
这项研究引入了一个四元逻辑 Booth 乘法器,减少了硬件需求并提高了速度. 新型设计通过减半操作位和优化部分产品压缩来提高效率.
科学领域:
- 数字电子产品数字电子产品
- 计算机算术 计算机算术
- 在VLSI的设计中,VLSI的设计
背景情况:
- 布斯算法和华莱士树方法加快了乘数速度.
- 与二进制逻辑相比,四进制逻辑将操作数和乘法位减半.
- 在四元逻辑中实现 Booth 可以减少乘数延迟和面积.
研究的目的:
- 设计一个以四元逻辑运行的第16阶 Booth 乘法器.
- 为四元符号数字表示和符号位确定提出新方法.
- 在四元逻辑中引入对四元多位和并行加倍器的直接编码.
主要方法:
- 设计了一种使用新型四级符号数字表示的四级 Booth 乘法器.
- 开发了一种直接编码技术,用于四级多位和四级并行加倍器.
- 实现了四元压缩机和一个信号位扩张防止技术.
- 在HSPICE中使用CNTFET模型模拟设计,以估计功率和延迟.
主要成果:
- 拟议的四级 Booth 乘法器设计被模拟.
- 估计了乘数器的最大静电消耗和延迟.
- 该设计旨在减少硬件复杂性和提高性能.
结论:
- 这项研究提出了一种可行的四级 Booth 乘法器设计.
- 提出的方法有可能减少延迟和乘数中的面积.
- 进一步评估功耗和延迟是基于模拟结果.
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