一个面积高效的读出电路,用于高SNR的三倍获取LOFIC CMOS图像传感器
Ai Otani1, Hiroaki Ogawa1, Ken Miyauchi1,2
1Research Organization of Science and Engineering, Ritsumeikan University, 1-1-1 Noji-Higashi, Kusatsu 525-8577, Japan.
Sensors (Basel, Switzerland)
|October 16, 2025
概括
本研究介绍了一种面积高效的读出电路,用于三倍增益的侧面溢出集成电容 (LOFIC) CMOS图像传感器 (CIS). 新设计改善了高动态范围 (HDR) 成像中的信号噪声比 (SNR) 性能.
科学领域:
- 电气工程 电气工程
- 计算机视觉 计算机视觉
- 半导体设备 半导体设备
背景情况:
- 高动态范围 (HDR) 成像对于先进的视觉应用至关重要.
- 侧向溢出集成电容 (LOFIC) CMOS图像传感器 (CIS) 通过结合高转换增益 (HCG) 和低转换增益 (LCG) 信号提供HDR功能.
- 由于LCG信号中的像素噪声,HCG到LCG信号切换点发生了信号噪声比率 (SNR) 的下降.
研究的目的:
- 为三倍增益的LOFIC CIS提出一个面积高效的读出电路.
- 为了解决双增益LOFIC CIS中的SNR下降问题.
- 为了提高CMOS图像传感器中的HDR成像性能.
主要方法:
- 开发了一种用于三倍增强LOFIC CIS的新型读出电路.
- 采用放大器和电容器共享技术用于HCG,中转换增益 (MCG) 和LCG信号处理.
- 使用0.18μm CMOS工艺制造了一个测试芯片.
主要成果:
- 对于拟议的读出电路,只实现了7.6%的空头面积.
- 与双增益LOFIC CIS读出电路相比,SNR下降幅度提高了8.05dB.
- 通过芯片制造证明了面积高效设计的可行性.
结论:
- 拟议的面积高效的读出电路有效处理三倍增益的LOFIC CIS信号.
- 该设计显著减轻了SNR下降,提高了HDR成像质量.
- 这一进步为下一代CMOS图像传感器提供了实用解决方案.
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