在二维半导体上的高κ介电范德瓦尔斯集成用于三维互补逻辑系统的二维半导体
Taeho Kang1,2, Joonho Park3, Seung Yong Lee1,2
1SKKU Advanced Institute of Nanotechnology (SAINT), Sungkyunkwan University, Suwon, Korea.
Nature communications
|November 25, 2025
概括
研究人员开发了一种新方法,将高-κ介电材料与二维半导体集成在一起,克服了表面反应性和可扩展性问题. 这种方法使高性能晶体管和对节能电子产品的互补逻辑成为可能.
科学领域:
- 材料科学 材料科学 材料科学
- 纳米技术纳米技术
- 半导体物理 半导体物理
背景情况:
- 集成高-κ介电和2D半导体是具有挑战性的,因为不反应的表面和沉积可扩展性.
- 传统的方法难以保持接口质量并实现可靠的设备性能.
研究的目的:
- 在二维半导体上开发一个通用的范德瓦尔斯 (vdW) 集成战略,用于2D半导体上的高电介质.
- 为了克服先进电子设备的表面反应性和沉积可扩展性的局限性.
主要方法:
- 一种新的干转移技术,使用HfSe2作为MoS2和WSe2.2上的高κ前体.
- 氧化等离子体将HfSe2转化为无形的HfO2,保持原子平面的VDW接口.
- 制造MoS2 n型场效应晶体管 (nFET) 和WSe2 p型场效应晶体管 (pFET).
主要成果:
- 实现了高κ介电堆 (κ ≈ 23) 与抑制的接口陷密度 (D_it ≈ 7-8 × 10^10 cm^-2 eV^-1).
- 已证明的nFET和pFET具有接近理想的下值波动 (≈60 mV/dec) 和可以忽略的歇斯底里斯 (≈3 mV).
- 成功集成互补逻辑电路,包括逆变器和环振荡器.
结论:
- 开发的VDW集成策略对于高性能2D半导体设备具有可扩展性和有效性.
- 这种方法使3D,节能逻辑技术的垂直集成成为可能.
- 这种方法为先进的纳米电子设备和系统铺平了道路.
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