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具有宽输入工作周期范围和低输出时钟工作周期错误的DLL设计

Binyu Qin¹, Haoyu Qin², Chenyu Fang¹

¹School of Integrated Circuits, Shandong University, Jinan 250101, China.

|November 27, 2025

概括

本研究引入了一种具有广泛工作周期范围的新型延时锁定循环 (DLL) 设计,这对于像DRAM这样的高速半导体芯片至关重要. 简单的架构确保了高级电子系统的高效时钟信号同步.

科学领域:

电气工程电气工程
计算机工程计算机工程
微电子学微电子学

背景情况:

现代半导体芯片需要更高的数据速率和精确的时钟信号.
现有的延时锁定循环 (DLL) 设计经常与广泛的输入时钟工作周期变化作斗争.
动态随机存储器 (DRAM) 系统需要强大的时钟解决方案.

研究的目的:

以简单的设计呈现一个新的DLL架构.
为了实现广泛的输入时钟工作周期范围,以提高适用性.
为了满足高速半导体应用的严格时钟要求.

主要方法:

设计了一个DLL,使用两个Bang-Bang相探测器 (BBPD).
该BBPD被用来独立调整分开时钟信号的上升和下降边缘.
实施和验证使用通过模拟的65nmCMOS工艺进行.

主要成果:

该DLL以3.2GHz的频率工作.
实现了从18%到72%的广泛输入时钟工作周期范围.
证明了0.6%的低最大输出时钟工作周期误差,高峰到高峰动率为15.73 ps,功耗为12.7 mW.

结论:

拟议的DLL设计为广泛的工作周期时钟同步提供了一个简单而有效的解决方案.
由于其性能指标,该设计非常适合用于高速应用,包括DRAM.
这项工作为下一代半导体集成电路提供了有价值的计时组件.

关键词:

在BBPD,BBPD是什么意思?DLL 是一个DLL.德拉姆 (DRAM) 是一个名字.双循环的双循环.

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