基于新型 4:2 压缩机和错误纠正逻辑的面积高效近似乘法器
Krishna Prashanth P1, Nithish Kumar V2
1School of Electronics Engineering, Vellore Institute of Technology, Vellore, 632014, India.
Scientific reports
|December 13, 2025
概括
这项研究引入了新的近似乘数,通过分区计算来提高能源效率和速度. 这些设计为容忍轻微精度损失的应用提供了显著的精度和性能增长.
科学领域:
- 计算机工程 计算机工程
- 数字电路 数字电路
- 估计计算 估计计算
背景情况:
- 乘法器对于算术电路至关重要,影响系统性能.
- 大致计算为那些能承受轻微准确性损失的应用程序提供了能源和速度的改进.
- 设计高效的乘法器需要平衡硬件复杂性和计算精度.
研究的目的:
- 引入新的近似乘法器架构.
- 为了提高能源效率,处理速度和硬件资源利用率.
- 为了在硬件效率和计算精度之间实现更好的权衡.
主要方法:
- 将乘数计算划分为准确的,近似的和较低的区域.
- 使用新的两台4:2压缩机与传统的算术电路进行部分产品压缩.
- 开发错误纠正逻辑来弥补不准确的情况.
- 使用基准错误指标和32nm CMOS技术的硬件合成来评估设计.
- 通过SSIM和PSNR评估进行实时图像乘法实验.
主要成果:
- 取得的平均改进:准确度为70.6%,能量延迟产品为60.4%,功率延迟产品为30.9%,延迟为41.6%.
- 与现有的近似倍数设计相比,证明了卓越的性能.
- 在图像乘法实验中显示出更高的SSIM和PSNR值,错误度降低.
结论:
- 拟议的近似乘数在准确性和性能指标方面提供了显著的改进.
- 这些新型架构在硬件效率和计算精度之间提供了卓越的权衡.
- 这些设计适用于需要高速,节能计算,精度损失最小的应用,如图像处理结果所证明的那样.
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