在FPGA上的高吞吐量和内存高效的管道关键值存储架构

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Xinshuo Wang^1,2, Lei Liu^1,2, Yifei Li^1,2

¹National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, China.

|December 31, 2025

概括

本研究介绍了一种基于FPGA的关键值存储 (KVS),以提高网络安全性能. 新型的多级多散列设计实现了高吞吐量和内存效率,适用于苛刻的网络应用程序.

科学领域:

计算机工程计算机工程
网络安全网络安全
硬件加速器硬件加速器

背景情况:

网络速度的增加需要高性能网络安全和监控系统.
关键值存储 (KVS) 是现代网络安全应用中的关键组件.
现有的KVS解决方案在吞吐量和存储利用方面面临挑战.

研究的目的:

提出并实施基于FPGA的KVS架构.
为了提高KVS的性能,特别是吞吐量和内存利用率.
在高速网络环境中解决当前KVS设计的局限性.

主要方法:

开发了一种多层次的多哈希方法来实现FPGA.
使用了脱存储设计,以提高内存效率.
实施了管道计划,以最大限度地提高运营吞吐量.

主要成果:

通过解存储实现了超过95%的内存利用率.
实现了每秒4亿个请求 (MRPS) 的高性能.
对于插入,查询和删除操作的低延迟保持在60秒.

结论:

拟议的基于FPGA的KVS有效地处理曲的工作负载,并避免错误的错误/插入.
这种架构为网络安全系统提供了显著的性能和功率效率改进.
该设计满足了高速网络流量对KVS性能日益增长的需求.

关键词:

在FPGA中,FPGA是指FPGA.在KVS中使用.硬件加速加速器硬件加速器通过平行管道输送.

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