晶圆尺度单层介电集成在原子薄的半导体上.
Zhenzhen Shen1, Haoqi Wu1, Chunsen Liu2
1State Key Laboratory of Integrated Chips and Systems, College of Integrated Circuits and Micro-Nano Electronics, Frontier Institute of Chip and System, Zhangjiang Fudan International Innovation Center, Fudan University, Shanghai, China.
Nature materials
|January 12, 2026
概括
研究人员开发了一种新的晶圆尺度单层三氧化 (MoO3) 介电器,用于超薄晶体管. 这一突破使得与二维材料进行强大的集成,实现亚纳米容量等效厚度 (CET) 以提高设备性能和可扩展性.
科学领域:
- 材料科学 材料科学 材料科学
- 半导体物理 半导体物理
- 纳米技术纳米技术
背景情况:
- 缩小金属氧化物半导体场效应晶体管 (MOSFET) 需要超薄的二维 (2D) 通道材料.
- 在2D材料上集成具有亚-1nm电容等效厚度 (CET) 的介电材料是一个重大挑战.
- 现有的方法难以在原子薄的半导体上实现均和坚固的介电层.
研究的目的:
- 开发一种可扩展的方法,将超低CET介电材料集成到二维材料上.
- 为了证明一种新的介电材料的有效性,用于先进的晶体管制造.
- 为了实现基于二维材料的晶体管的工业部署.
主要方法:
- 通过从二硫化 (MoS2) 转化单层三氧化物 (MoO3) 的晶圆尺度合成.
- 无集成MoO3与原子薄的半导体.
- 高-κ介电物的沉积 (例如,HfO2) 在原子平面MoO3表面.
- 使用MoO3/HfO2介电堆制造和表征顶端2D晶体管.
主要成果:
- 在2D晶体管上使用MoO3/HfO2介电器实现了亚-1nm CET (0.96nm).
- 证明了高的开/关比 (p型为6.5 × 10^6,n型为3.2 × 10^8) 和急剧的下值波动 (p型为60.8 mV/dec,n型为63.1 mV/dec).
- 在1024个设备阵列中,经过验证的高设备收益率 (92.2%).
- 使用单层MoO3作为顶级介电体,超级缩放的CET为0.64nm,符合低功率泄漏标准 (1.5 × 10^-2 A/cm^2).
结论:
- 单层MoO3提供了一个可扩展的途径,用于将超低CET介电材料与2D材料集成.
- 开发的介电集成策略显著提高了2D晶体管的性能.
- 这项工作代表了对2D半导体设备的工业应用的关键进步.
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