一个宽带不匹配校准原型,适用于时间间隔模拟到数字转换器系统的特定应用集成电路
Jiacheng Guo1,2, Jiajun Qin1,2, Zhikang Chen1,2
1State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei 230026, China.
The Review of scientific instruments
|January 29, 2026
概括
本研究引入了时间间隔模拟数字转换器 (TIADC) 系统的新设计,显著降低了资源消耗. 提出的方法实现了超过80%的面积和功率的减少,优于基于现场可编程门阵列 (FPGA) 的系统.
科学领域:
- 电气工程 电气工程
- 集成电路设计 集成电路设计
- 信号处理 信号处理
背景情况:
- 时间间隔模拟数字转换器 (TIADC) 对于高速数据采集至关重要.
- 现场可编程门阵列 (FPGA) 常用于TIADC数字校准,但在功耗,复杂性和资源利用方面存在挑战.
研究的目的:
- 提出一个系统的设计方法,以减少TIADC系统的资源消耗.
- 开发一个资源高效的数字校准过器,并整合一个简化的时钟生成电路.
- 为了证明拟议的架构对校准不同分辨率的高速ADC的有效性.
主要方法:
- 通过分析过器系数和优化计算错误分配,开发了一种资源效率高的数字校准过器.
- 集成了一个多相采样时钟生成电路,具有可调节的延迟,以简化系统实现和调节时间不匹配.
- 在130纳米CMOS技术中实现了原型应用特定集成电路 (ASIC),与多达四个5Gsps ADC接口.
主要成果:
- 数字校准波器的面积和功耗减少了80%以上.
- 原型ASIC消耗11.5W,有效校准高速ADC中的宽带不匹配错误.
- 与相似的现代过程节点中的FPGA实现相比,预计将减少90%以上的功耗,实施复杂性较低.
结论:
- 提出的系统设计方法显著降低了TIADC系统的资源消耗.
- 该ASIC实现验证了数字校准波器和时钟生成电路的有效性.
- 与基于FPGA的方法相比,开发的方法为高速ADC校准提供了更节能,更简单的解决方案.
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