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Updated: Feb 7, 2026

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高速双精度高效计算和设计 维德式乘法器架构

Aruru Sai Kumar1, G Sahitya2, Rambabu Kusuma3

  • 1School of Electronics Engineering, VIT-AP University, Amaravati, Andhra Pradesh, India.

Scientific reports
|February 5, 2026
PubMed
概括

本研究介绍了一种高效的双精度浮点乘法器,使用维达数学. 这种新的设计显著降低了硬件复杂性,并提高了数字信号处理和CNN应用的性能.

关键词:
区域和延迟时间双精度维达式乘法器 (DPVM) 是一种双精度维达式乘法器.浮点乘法 浮点乘法 浮点乘法主位比特乘法乘法.维里洛格高清高清版这就是Zynq FPGA.

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