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一个端到端的设计和模拟方法来评估PCIe通道中的包诱导信号完整性退化

Siwook Park¹, Uichan Kim¹, Jonghyun Lee¹

¹Department of Semiconductor System Engineering, Sejong University, Seoul 05006, Republic of Korea.

|February 27, 2026

概括

包装设计显著影响信号完整性 (SI) 在高速通道,如外围组件互连快速 (PCIe) 5.0.0. 端到端模拟对于准确预测由包间断引起的系统级SI退化至关重要.

科学领域:

电气工程电气工程
计算机工程计算机工程
材料科学材料科学材料科学

背景情况:

高速数字系统依赖于强大的信号完整性 (SI).
包装设计引入了影响道性能的关键不连续性.
外围组件互联快速连接 (PCIe) 5.0需要先进的SI分析.

研究的目的:

开发一个端到端的模拟方法来评估PCIe 5.0通道中的包诱导的SI退化.
评估各种包级因素对系统级SI的影响.
为包装和通道联合设计提供框架.

主要方法:

包装,印刷电路板 (PCB) 和附加卡 (AIC) 结构的综合模拟.
分析阻抗不匹配,曲线路由和通过条的单独和组合效应.
插入损失的评估,内对曲和眼睛图.

主要成果:

局部化的包不连续性通过端到端通道传播和复合.
由于包装损伤,系统级眼睛图的显著减少.
包装诱导的SI降解需要端到端的道分析,而不仅仅是包装级别的评估.

结论:

软件包设计的选择对PCIe 5.0.0中的系统级SI具有重要影响.
完整的端到端模拟方法对于准确的SI预测至关重要.
拟议的方法有助于下一代高速包装和通道联合设计.

关键词:

这是PCIe PCIe.终端到终端的终端.包装引起的降解.信号完整性 (SI) 是指信号完整性.

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