3级垂直堆叠Si纳米板GAApFETs与低温接口处理用于冷应用
Lewen Qian1, Tao Liu1, Meicheng Liao1
1State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai 200433, China.
Nanomaterials (Basel, Switzerland)
|March 13, 2026
概括
这项研究引入了一种新型的冷性CMOS纳米板晶体管,使用O基被动化来克服下值摆动和. 这一创新能够显著减少泄漏电流,并提高低温节能计算的性能.
科学领域:
- 材料科学与工程 材料科学与工程
- 半导体设备物理 半导体设备物理
- 低温电子产品 低温电子产品
背景情况:
- 低温CMOS技术对于高性能计算至关重要,其目标是超越博尔兹曼极限并扩展摩尔定律.
- 在冷温度下带尾效应会导致设备的下值摆动 (SS) 和,阻碍性能.
- 现有的方法在低温下对复杂的3D结构进行界面缺陷控制.
研究的目的:
- 为了呈现一个为低温操作优化的3个垂直堆叠的门全方位纳米板 (NS) 晶体管.
- 为了减轻带尾效应和SS和,使用室温O激素接口被动化.
- 为了增强下值切换,减少泄漏电流,并在冷温度下提高设备性能.
主要方法:
- 制造一个3个垂直堆叠的门全包围纳米板 (NS) 晶体管.
- 应用室温O基被动化以尽量减少蚀刻引起的损伤和被动化接口缺陷.
- 使用技术来评估接口层厚度,表面粗度和接口陷密度的结构性表征.
主要成果:
- 实现了0.76纳米厚的统一接口层,表面粗度低 (0.103纳米) 和接口陷密度低 (2.72 × 1011 cm-2·eV-1).
- 有效地减轻了SS和,在4.5K时达到15.4mV/dec的和SS.
- 在77K下降到1pA/μm以下 (0.18pA/μm在4.5K),降低了25.4%的DIBL,并在4.5K时提高了9%的Gm峰值.
结论:
- 室温O基被动化在优化冷NS FET的接口方面非常有效.
- 开发的NS FET表现出卓越的下值切换,显著减少泄漏,并在冷温度下提高性能.
- 这种界面优化强烈支持cryo-CMOS作为未来节能计算应用的可行技术.
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