在 IIoT 应用程序的管道 ADC 中用于线性增强的减法二度辅助背景校准
Shang Xu1, Shuwen Liang1, Jinbin Li1
1School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, China.
Sensors (Basel, Switzerland)
|March 14, 2026
概括
这项研究引入了一种用于模拟数字转换器 (ADC) 的新型减法校准. 该技术显著提高了无虚假动态范围 (SFDR),对信号与噪声比 (SNDR) 有最小的影响.
科学领域:
- 电气工程 电气工程
- 集成电路设计 集成电路设计
- 信号处理 信号处理
背景情况:
- 管道式模拟数字转换器 (ADC) 对于高速数据采集至关重要.
- 在ADC中的非线性,如微分非线性 (DNL) 和积分非线性 (INL),降低性能.
- 传统的校准方法可能是复杂和耗电的.
研究的目的:
- 介绍2GS/s12位管道ADC的减法-dither辅助背景校准技术.
- 通过对非线性错误进行脱相关,改进无假动态范围 (SFDR).
- 评估动对信号与噪声和扭曲比率 (SNDR) 和静态线性的影响.
主要方法:
- 将一个7位的伪随机模拟器注入闪光灯并乘以数字对模拟转换器 (MDAC) 阶段.
- 在28nmCMOS工艺中设计和模拟ADC,使用1V电源.
- 布局后模拟以评估在近尼奎斯特输入频率下的性能改进.
主要成果:
- 在SFDR中,通过dithering.实现了10.2dB的改进,从73.8dB提高到84.4dB.
- 信号对噪声和扭曲比率 (SNDR) 的降解是最小的 (0.5dB),导致62.3dB和10.1有效比特 (ENOB).
- 静态线性得到了改进,DNL和INL分别优化为±0.54 LSB和±0.88 LSB.
- 基于dither的校准引入了不到2mW的额外功耗.
结论:
- 减法-dither辅助背景校准技术有效地增强了ADC SFDR.
- 该方法提供了一种低功耗的解决方案,用于改善ADC线性,而不会造成显著的SNDR惩罚.
- 这种技术适用于高级CMOS工艺中的高速,高分辨率ADC应用.
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