基于带偏差的2D MoS2晶体管的通用逻辑块
Xiaofu Wei1,2, Zhangyi Chen1,2, Kuanglei Chen1,2
1Academy for Advanced Interdisciplinary Science and Technology, Key Laboratory of Advanced Materials and Devices for Post-Moore Chips Ministry of Education, State Key Laboratory for Advanced Metals and Materials, University of Science and Technology Beijing, Beijing, PR China.
Nature communications
|March 16, 2026
概括
这项研究引入了一种新的通用逻辑块 (GLB),用于用于先进集成电路的偏差门式场效应晶体管 (BG-FET). 这些BG-FET能够实现可重新配置的逻辑操作,使用的晶体管比传统的CMOS技术少得多.
科学领域:
- 材料科学 材料科学 材料科学
- 电气工程 电气工程
- 计算机科学 计算机科学
背景情况:
- 将二维半导体与CMOS集成为下一代电路的关键.
- 挑战包括有限的二维半导体极性调制和CMOS架构限制.
研究的目的:
- 开发一种新的通用逻辑块 (GLB),用于可重新配置的逻辑操作.
- 为了克服当前2D半导体集成和CMOS架构的局限性.
主要方法:
- 使用了带偏差门的二硫化物晶体管 (BG-FET).
- 设计了一个包括四个BG-FET用于可重新配置逻辑的GLB.
- 级联 GLBs 创建翻转式电路和算术逻辑单元.
主要成果:
- BG-FETs展示了具有偏差操纵的值适应性场效应特征.
- 四个BG-FET GLB实现了可重新配置的逻辑操作 (门,半,MUX,编码器,SRAM).
- 与复杂电路的CMOS相比,实现了超过60%的晶体管数量节省.
结论:
- 基于BG-FET的GLB提供了一个有前途的CMOS后集成技术.
- 这种方法显著减少了复杂逻辑函数的晶体管数量.
- 能够实现高效且可重新配置的集成电路设计.
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