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A VLSI design of a pipeline Reed-Solomon decoder
H M Shao1, T K Truong, L J Deutsch
1Jet Propulsion Laboratory, California Institute of Technology, Pasadena 91109, USA.
IEEE Transactions on Computers. Institute of Electrical and Electronics Engineers
|May 1, 1985
Abstract:
A pipeline structure of a transform decoder similar to a systolic array is developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error-locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new coder is regular and simple, and naturally suitable for VLSI implementation. An example illustrating both the pipeline and systolic array aspects of this decoder structure is given for a RS code.