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Better Circuits for Binary Polynomial Multiplication.

Magnus Gaudal Find1, René Peralta2

  • 1National Institute of Standards and Technology, Gaithersburg, MD 20899.

IEEE Transactions on Computers. Institute of Electrical and Electronics Engineers
|October 4, 2019
PubMed
Summary
This summary is machine-generated.

Researchers developed a new method for Karatsuba-like algorithms in binary polynomial multiplication. This approach improves circuit efficiency for multiplying polynomials over F2, with practical applications demonstrated.

Keywords:
Binary polynomial multiplicationcircuitssymmetric bilinear circuits

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Area of Science:

  • Computer Science
  • Computational Mathematics
  • Algebraic Complexity Theory

Background:

  • Polynomial multiplication is a fundamental operation in computer science and cryptography.
  • Efficient algorithms for polynomial multiplication over finite fields, such as F2, are crucial for various applications.
  • Existing methods, like Karatsuba's algorithm, offer improvements over naive multiplication but can be further optimized.

Purpose of the Study:

  • To develop a novel and simplified approach for describing Karatsuba-like algorithms for polynomial multiplication over F2.
  • To restrict the search for efficient circuits to a specific class termed 'symmetric bilinear' circuits.
  • To derive improved recurrences for the number of gates required in circuits for multiplying binary polynomials.

Main Methods:

  • Introduced a new framework for Karatsuba-like algorithms tailored for polynomials over F2.
  • Focused on symmetric bilinear circuits, where AND gates compute specific bilinear functions.
  • Derived new recurrence relations for M(kn), the gate count for multiplying kn-term polynomials.

Main Results:

  • Achieved improved recurrences for M(kn) for k = 4, 5, 6, and 7.
  • Successfully built and verified circuits for n-term binary polynomial multiplication for practically relevant values of n.
  • Made implemented circuits for n up to 100 publicly available.

Conclusions:

  • The developed techniques offer a more efficient way to design circuits for binary polynomial multiplication.
  • The focus on symmetric bilinear circuits provides a structured approach to finding optimized algorithms.
  • The availability of implemented circuits facilitates further research and practical use in areas requiring efficient polynomial arithmetic.