Mapping of neural networks onto the memory-processor integrated architecture

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Architecture

Background:

• Artificial Neural Networks (ANNs) require efficient hardware architectures for complex computations.
• Existing architectures like SIMD arrays and hypercubes have limitations in ANNs processing.

Purpose of the Study:

• To propose an effective memory-processor integrated architecture, the Memory-Based Processor Array for Artificial Neural Networks (MPAA).
• To develop mapping algorithms for implementing multilayer perceptron with backpropagation learning on the MPAA.
• To demonstrate the superiority of MPAA over existing architectures.

Main Methods:

• Designed MPAA with hybrid row and column decoding for efficient local memory access.
• Developed mapping algorithms supporting neuron and layer level parallelisms for pipelined operations.
• Conducted performance evaluation comparing cost and computation steps against various architectures.

Main Results:

• MPAA architecture integrates seamlessly with host systems via memory interface.
• Hybrid decoding enables efficient matrix-by-vector operations crucial for ANNs.
• Pipelined execution of learning and recall phases achieved through parallel algorithms.

Conclusions:

• The proposed MPAA architecture and its associated algorithms significantly outperform previous approaches.
• MPAA offers a more efficient solution for ANNs computation, particularly for multilayer perceptrons.
• This architecture provides a scalable and high-performance platform for future AI hardware development.