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Mixed microprocessor-random logic approach for innovative pacing systems.

G Gaggini1, B Garberoglio, L Silvestri

  • 1Sorin Biomedica, Saluggia, Italy.

Pacing and Clinical Electrophysiology : PACE
|November 1, 1992
PubMed
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This study presents a mixed microprocessor-random logic approach for cardiac pacing integrated circuits (ICs). This design optimizes performance and reduces complexity for advanced pacing system functions.

Area of Science:

  • Biomedical Engineering
  • Embedded Systems Design

Background:

  • Modern cardiac pacing systems require sophisticated integrated circuits (ICs) for sensor data processing and complex timing management.
  • Fully microprocessor-based solutions face limitations in operating speed and timing accuracy due to sequential processing and low clock frequencies.
  • Random logic structures, while fast, can be less flexible and more complex for implementing advanced pacing algorithms.

Purpose of the Study:

  • To investigate a mixed microprocessor-random logic architecture for cardiac pacing ICs.
  • To overcome the limitations of purely microprocessor-based or random logic designs in pacing systems.
  • To enhance the flexibility and real-time performance of integrated circuits for cardiac pacing.

Main Methods:

  • Developed a hybrid architecture combining a microprocessor core with random logic peripherals.

Related Experiment Videos

  • Utilized the microprocessor for high-level, non-real-time operations like setup and data processing.
  • Employed random logic for critical, real-time timing functions.

    • Main Results:

    • The mixed approach effectively balances the flexibility of microprocessors with the speed of random logic.
    • Critical timing aspects requiring high accuracy are managed by dedicated random logic.
    • High-level operations are handled by the microprocessor, optimizing resource utilization.

    Conclusions:

    • The mixed microprocessor-random logic architecture offers a viable solution for advanced cardiac pacing ICs.
    • This approach mitigates timing inaccuracies associated with full microprocessor designs.
    • It enables the development of less complex and more performant integrated circuits for sophisticated pacing systems.