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An efficient method for parallel CRC automatic generation.

Hong-Sheng Chen1, Wei-Cheng Zhang, Yong Wang

  • 1Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China. hansomchen@zju.edu.cn

Journal of Zhejiang University. Science
|July 16, 2003
PubMed
Summary
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A new State Transition Equation (STE) method automatically generates parallel Cyclic Redundancy Check (CRC) circuits. This approach improves timing and reduces synthesis time compared to traditional methods.

Area of Science:

  • Computer Engineering
  • Digital Circuit Design
  • Error Detection Codes

Background:

  • Cyclic Redundancy Check (CRC) is crucial for error detection in data transmission.
  • Existing methods for parallel CRC circuit generation can be complex and time-consuming.
  • Optimization of CRC circuits impacts performance and resource utilization.

Purpose of the Study:

  • To present a novel State Transition Equation (STE) based method for automatic parallel CRC circuit generation.
  • To enable the creation of parallel CRC circuits for any generator polynomial and parallelism level.
  • To compare the proposed method against the cascading method for efficiency and performance.

Main Methods:

  • Utilizing State Transition Equations (STE) to define and generate parallel CRC circuit structures.

Related Experiment Videos

  • Implementing partial optimization of the generated circuits before synthesis.
  • Testing the generated circuits in a practical Local Area Network (LAN) transceiver.

    • Main Results:

    • The STE-based method successfully generates parallel CRC circuits for diverse specifications.
    • Generated circuits demonstrate proper functionality within a LAN transceiver.
    • The proposed method yields superior timing results compared to the cascading method.
    • Significant reduction in synthesis time was observed using the STE-based approach.

    Conclusions:

    • The State Transition Equation (STE) based method offers an efficient and effective way to automatically design parallel CRC circuits.
    • This method provides advantages in terms of timing performance and reduced synthesis effort.
    • The approach is validated by its successful implementation and performance in a real-world application.