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Low-cost and nanoscale non-volatile memory concept for future silicon chips
Martijn H R Lankhorst1, Bas W S M M Ketelaars, R A M Wolters
1Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands. martijn.lankhorst@philips.com
Nature Materials
|March 15, 2005
Summary
Researchers developed a new non-volatile memory using phase-change materials. This technology offers faster speeds and lower power consumption for advanced semiconductor applications.
Area of Science:
- Materials Science
- Electrical Engineering
- Computer Engineering
Background:
- Non-volatile flash memories are crucial for integrated circuits, retaining data without power.
- The semiconductor industry seeks advanced non-volatile memories with enhanced performance and scalability.
- Current flash memory technologies face limitations in speed and cell size reduction.
Purpose of the Study:
- To demonstrate a novel semiconductor memory concept utilizing phase-change materials.
- To explore the potential of nanoscale phase-change lines for improved memory performance.
- To assess the feasibility of integrating this new memory into existing CMOS processes.
Main Methods:
- Fabrication of individual memory cells based on narrow lines of phase-change material.
- Programming the phase-change material between two resistive states using low-power current pulses.
- Utilizing a doped-SbTe phase-change material for enhanced performance characteristics.
Main Results:
- Reversible programming of the phase-change material between two states on a nanosecond timescale.
- Demonstrated improved speed and reduced power consumption by scaling phase-change lines to the nanometre scale.
- Confirmed the viability of the doped-SbTe material for high-performance memory applications.
Conclusions:
- The demonstrated phase-change memory concept offers a promising alternative to current non-volatile memory technologies.
- Nanoscale engineering of phase-change materials significantly enhances memory speed and energy efficiency.
- The simplicity of the proposed design suggests potential for straightforward integration into standard CMOS manufacturing flows.