FPGA implementation of self organizing map with digital phase locked loops.

Area of Science:

• Artificial Intelligence
• Hardware Engineering
• Signal Processing

Background:

• Self-organizing maps (SOMs) are widely used in various applications.
• A new SOM hardware architecture utilizing phase-modulated pulse signals and digital phase-locked loops (DPLLs) was previously proposed.
• DPLLs offer computational similarities to SOM operations, making them suitable for hardware implementation.

Purpose of the Study:

• To discuss the hardware implementation of the DPLL SOM architecture.
• To redesign components for effective and reduced circuit size.
• To describe and implement the proposed SOM architecture on a field-programmable gate array (FPGA).

Main Methods:

• The DPLL SOM architecture was described using VHDL (VHSIC Hardware Description Language).
• The design was implemented on a field-programmable gate array (FPGA).
• Component redesigns were performed to optimize circuit size.

Main Results:

• The feasibility of the hardware implementation was verified through experiments.
• The proposed FPGA-based SOM demonstrated good quantization capability.
• The implemented circuit size was significantly reduced.

Conclusions:

• The DPLL SOM architecture is feasible for hardware implementation on FPGAs.
• The redesigned components contribute to a smaller circuit size.
• The FPGA implementation offers efficient computation and good quantization for SOM applications.