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A Survey of Hardware Self-Organizing Maps.
IEEE Transactions on Neural Networks and Learning Systems
|March 16, 2022
Summary
Hardware implementations of Self-Organizing Feature Maps (SOMs) are surveyed to address computational costs. This review covers architectures and optimizations, paving the way for real-time big data and IoT applications.
Area of Science:
- Computer Science
- Artificial Intelligence
- Hardware Architecture
Background:
- Self-organizing feature maps (SOMs) are vital for unsupervised clustering and dimensionality reduction.
- Their topology preservation makes them suitable for Internet of Things (IoT) and big data (BD).
- High computational costs hinder real-time online processing, limiting SOMs to offline applications.
Purpose of the Study:
- To survey existing hardware (HW) implementations of SOMs.
- To analyze common computing blocks, architectures, and design choices in HW SOMs.
- To identify challenges and trends for adopting HW SOMs as accelerators.
Main Methods:
- Literature review of hardware SOM implementations.
- Analysis of reported computing blocks, architectures, and optimization techniques.
- Overview of challenges and future trends in the field.
Main Results:
- Identified widely used computing blocks and architectures for hardware SOMs.
- Detailed various adaptation and optimization techniques for hardware implementations.
- Provided insights into challenges and trends for ubiquitous adoption.
Conclusions:
- Hardware implementations are crucial for overcoming SOM computational limitations.
- Further research in HW SOM accelerators can enable real-time processing for IoT and big data.
- This survey serves as a valuable resource for researchers in AI, hardware architecture, and system design.
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