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Related Experiment Videos

FPGA implementation of self organizing map with digital phase locked loops.

Hiroomi Hikawa1

  • 1Department of Computer Science and Intelligent Systems, Oita University, Oita 870-1192, Japan. hikawa@csis.oita-u.ac.jp

Neural Networks : the Official Journal of the International Neural Network Society
|August 13, 2005
PubMed
Summary

This study presents a novel hardware implementation of the self-organizing map (SOM) using digital phase-locked loops (DPLLs). The field-programmable gate array (FPGA) based design demonstrates efficient computation and small circuit size for advanced machine learning applications.

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Area of Science:

  • Artificial Intelligence
  • Hardware Engineering
  • Signal Processing

Background:

  • Self-organizing maps (SOMs) are widely used in various applications.
  • A new SOM hardware architecture utilizing phase-modulated pulse signals and digital phase-locked loops (DPLLs) was previously proposed.
  • DPLLs offer computational similarities to SOM operations, making them suitable for hardware implementation.

Purpose of the Study:

  • To discuss the hardware implementation of the DPLL SOM architecture.
  • To redesign components for effective and reduced circuit size.
  • To describe and implement the proposed SOM architecture on a field-programmable gate array (FPGA).

Main Methods:

  • The DPLL SOM architecture was described using VHDL (VHSIC Hardware Description Language).

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  • The design was implemented on a field-programmable gate array (FPGA).
  • Component redesigns were performed to optimize circuit size.
  • Main Results:

    • The feasibility of the hardware implementation was verified through experiments.
    • The proposed FPGA-based SOM demonstrated good quantization capability.
    • The implemented circuit size was significantly reduced.

    Conclusions:

    • The DPLL SOM architecture is feasible for hardware implementation on FPGAs.
    • The redesigned components contribute to a smaller circuit size.
    • The FPGA implementation offers efficient computation and good quantization for SOM applications.