1Department of Computer Science and Intelligent Systems, Oita University, Oita 870-1192, Japan. hikawa@csis.oita-u.ac.jp
This study presents a novel hardware implementation of the self-organizing map (SOM) using digital phase-locked loops (DPLLs). The field-programmable gate array (FPGA) based design demonstrates efficient computation and small circuit size for advanced machine learning applications.
You might also read
Articles linked to this work by shared authors, journal, and citation graph.
Area of Science:
Background:
Purpose of the Study:
Main Methods:
Main Results:
Conclusions: