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Updated: Aug 14, 2026

Flow-assisted Dielectrophoresis: A Low Cost Method for the Fabrication of High Performance Solution-processable Nanowire Devices
Published on: December 7, 2017
Low operating voltage single ZnO nanowire field-effect transistors enabled by self-assembled organic gate
Sanghyun Ju1, Kangho Lee, David B Janes
1School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907, USA.
Abstract:
The development of nanowire transistors enabled by appropriate dielectrics is of great interest for flexible electronic and display applications. In this study, nanowire field-effect transistors (NW-FETs) composed of individual ZnO nanowires are fabricated using a self-assembled superlattice (SAS) as the gate insulator. The 15-nm SAS film used in this study consists of four interlinked layer-by-layer self-assembled organic monolayers and exhibits excellent insulating properties with a large specific capacitance, 180 nF/cm2, and a low leakage current density, 1 x 10(-8) A/cm2. SAS-based ZnO NW-FETs display excellent drain current saturation at Vds = 0.5 V, a threshold voltage (Vth) of -0.4 V, a channel mobility of approximately 196 cm2/V s, an on-off current ratio of approximately 10(4), and a subthreshold slope of 400 mV/dec. For comparison, ZnO NW-FETs are also fabricated using 70-nm SiO2 as the gate insulator. Implementation of the SAS gate dielectric reduces the NW-FET operating voltage dramatically with more than 1 order of magnitude enhancement of the on-current. These results strongly indicate that SAS-based ZnO NW-FETs are promising candidates for future flexible display and logic technologies.
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