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Related Experiment Video

Updated: Jul 17, 2026

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates
08:07

Ultrahigh Density Array of Vertically Aligned Small-molecular Organic Nanowires on Arbitrary Substrates

Published on: June 18, 2013

Layer-by-layer assembly of nanowires for three-dimensional, multifunctional electronics.

Ali Javey1, SungWoo Nam, Robin S Friedman

  • 1Department of Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts 02138, USA.

Nano Letters
|February 3, 2007
PubMed
Summary

Researchers developed a general method for 3D electronics using nanowire (NW) assembly. This approach enables the creation of complex, multifunctional devices with reproducible, high-performance characteristics across multiple stacked layers.

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Area of Science:

  • Materials Science
  • Nanotechnology
  • Electrical Engineering

Background:

  • Advancements in nanotechnology have enabled the development of nanowire (NW) building blocks for electronic devices.
  • Creating complex three-dimensional (3D) electronic structures with reproducible performance remains a significant challenge.

Purpose of the Study:

  • To present a general approach for fabricating 3D multifunctional electronics using layer-by-layer assembly of NWs.
  • To demonstrate the performance and stability of NW-based transistors and memory elements in a 3D stacked architecture.

Main Methods:

  • Layer-by-layer assembly of germanium/silicon (Ge/Si) core/shell nanowires (NWs).
  • Fabrication of vertically stacked multi-NW field-effect transistors (FETs) and single-NW FET structures.

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Last Updated: Jul 17, 2026

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08:07

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A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics

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  • Integration of NWs into 3D multifunctional circuitry including inverter logic gates and floating gate memory elements on plastic substrates.

    • Main Results:

    • Reproducible, high-performance device characteristics were achieved in stacked Ge/Si NW FETs across ten sequential layers.
    • Device performance remained unaffected by sequential stacking, demonstrating uniformity.
    • Stable operation of NW floating gate memory elements and signal inversion with gain > 1 up to 50 MHz were demonstrated.

    Conclusions:

    • The layer-by-layer NW assembly approach enables the creation of complex, multilayer 3D electronics.
    • This method facilitates the integration of diverse NW-based devices for advanced functionalities.
    • Future development could lead to increasingly sophisticated 3D electronic systems with enhanced capabilities.