The impact of arithmetic representation on implementing MLP-BP on FPGAs: a study.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Acceleration

Background:

• Multilayer perceptrons (MLP-BP) are widely used neural networks.
• Implementing neural networks on hardware like FPGAs requires efficient arithmetic representations.
• Floating-point (FLP) and fixed-point (FXP) formats are common choices with trade-offs.

Purpose of the Study:

• To analyze arithmetic representations for MLP-BP neural networks on FPGAs.
• To compare the performance and resource utilization of FLP and FXP formats.
• To investigate the impact of precision and range on FPGA implementation.

Main Methods:

• Detailed examination of arithmetic representations for MLP-BP on FPGAs.
• Study of both floating-point (FLP) and fixed-point (FXP) data formats.
• Development of a generic VHDL program for experimental analysis of various formats and designs.

Main Results:

• Fixed-point (FXP) MLP-BP implementations consume less FPGA real estate compared to FLP.
• FXP format requires fewer clock cycles for MLP-BP execution than FLP.
• Performance and area trade-offs were evaluated based on precision and range.

Conclusions:

• FXP arithmetic representations provide a more efficient solution for implementing MLP-BP neural networks on FPGAs.
• Choosing FXP over FLP can lead to significant reductions in hardware resources and processing time.
• The study highlights the importance of selecting appropriate arithmetic formats for hardware-accelerated neural networks.