Dynamically reconfigurable silicon array of spiking neurons with conductance-based synapses

Area of Science:

• Neuroscience
• Computer Engineering
• Artificial Intelligence

Background:

• Spiking neural networks (SNNs) are computational models inspired by biological neurons.
• Emulating large-scale SNNs requires specialized hardware for efficient simulation.
• Existing hardware may lack flexibility in neuron and synapse programmability.

Purpose of the Study:

• To present a novel mixed-signal very large scale integration (VLSI) chip for large-scale emulation of spiking neural networks.
• To detail the design and characterization of silicon neurons with programmable synaptic connectivity.
• To demonstrate the chip's utility in emulating complex neural dynamics.

Main Methods:

• Design and fabrication of a mixed-signal VLSI chip with 2400 silicon neurons.
• Implementation of a discrete-time single-compartment neuron model with analog membrane dynamics.
• Utilizing an address-event (AE) transceiver architecture with an asynchronous event-driven digital bus.
• External routing of events using dynamically programmable random-access memory for synaptic parameters.

Main Results:

• Characterization of a 3 mm x 3 mm chip fabricated in 0.5-microm CMOS technology.
• Demonstration of fully programmable and reconfigurable synaptic connectivity for each neuron.
• Successful emulation of attractor dynamics and neural activity waves during sleep in rat hippocampus models.

Conclusions:

• The developed VLSI chip offers a powerful platform for large-scale SNN emulation.
• The chip's reconfigurable architecture facilitates the study of complex neural dynamics.
• This hardware advancement can accelerate research in computational neuroscience and artificial intelligence.