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Related Concept Videos

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Voltage-gated Ion Channels

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Voltage-gated ion channels are transmembrane proteins that open and close in response to changes in the membrane potential. They are present on the membranes of all electrically excitable cells such as neurons, heart, and muscle cells.
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Voltage01:13

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The movement of electrons in a conductor requires some form of energy or work, usually provided by an external force, like a battery. This force is called the electromotive force or voltage. The voltage between two points, referred to as points "a" and "b," in an electric circuit is the energy (or work) needed to move a unit charge from point "a" to point "b," and this relationship is expressed mathematically as
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Related Experiment Video

Updated: Jan 23, 2026

Voltage-Dependent Potassium Current Recording on H9c2 Cardiomyocytes via the Whole-Cell Patch-Clamp Technique
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Voltage-Dependent Potassium Current Recording on H9c2 Cardiomyocytes via the Whole-Cell Patch-Clamp Technique

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A 1024-Channel Hybrid Voltage/Current-Clamp Neural Interface System-on-Chip With Dynamic Incremental SAR Acquisition.

Jun Wang, Omowuyi Olajide, Akshay Paul

    IEEE Transactions on Biomedical Circuits and Systems
    |January 21, 2026
    PubMed
    Summary

    This study introduces a novel neural interface system-on-chip (NISoC) for high-throughput neuroscience research. It achieves record energy efficiency for neural recording and stimulation with integrated data compression capabilities.

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    Area of Science:

    • Neuroscience
    • Electrical Engineering
    • Materials Science

    Background:

    • High-throughput, multi-modal recording and stimulation are crucial for neuroscience.
    • On-chip data compression is essential for reducing data volume in neural interfaces.
    • Existing neural interfaces face challenges in balancing area, energy efficiency, and noise performance.

    Purpose of the Study:

    • To develop a neural interface system-on-chip (NISoC) with high channel count and efficiency.
    • To enable simultaneous high-resolution electrical recording and stimulation.
    • To integrate on-chip data acquisition and compression for reduced data volume.

    Main Methods:

    • Fabrication of a 1,024-channel NISoC using 65 nm CMOS technology.
    • Integration of a 32x32 electrode array with analog front-ends supporting voltage and current clamping.
    • Implementation of 32 dynamic incremental SAR ADCs for on-chip data acquisition.

    Main Results:

    • Achieved record noise-energy efficiency with 0.81 µW/channel power consumption and 8.8 µVrms input-referred voltage noise.
    • Demonstrated high-throughput data acquisition at 25 Msps with 11 effective number of bits (ENOB).
    • Achieved an energy efficiency of 2 fJ/level for data acquisition.

    Conclusions:

    • The developed NISoC offers a significant advancement in neural interface technology for neuroscience research.
    • The system provides high-resolution, high-throughput electrophysiology with exceptional noise-energy efficiency.
    • Integrated spike detection in ADCs paves the way for future on-chip neural data compression.