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A memetic algorithm for VLSI floorplanning.

Maolin Tang1, Xin Yao

  • 1Queensland University of Technology, Brisbane 4001, Australia. m.tang@qut.edu.au

IEEE Transactions on Systems, Man, and Cybernetics. Part B, Cybernetics : a Publication of the IEEE Systems, Man, and Cybernetics Society
|February 7, 2007
PubMed
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This study introduces a novel memetic algorithm (MA) for optimizing very large scale integrated-circuit (VLSI) chip design. The MA efficiently finds optimal or near-optimal VLSI floorplans, crucial for chip performance and size.

Area of Science:

  • Computer Science
  • Electrical Engineering
  • Artificial Intelligence

Background:

  • VLSI floorplanning is critical for chip performance, size, yield, and reliability.
  • The computational complexity of VLSI floorplanning classifies it as an NP-hard problem.
  • Existing methods may struggle with efficiency and solution quality for complex floorplanning tasks.

Purpose of the Study:

  • To present a novel memetic algorithm (MA) for the nonslicing, hard-module VLSI floorplanning problem.
  • To enhance the exploration and exploitation balance in genetic search for VLSI design.
  • To provide an efficient computational approach for optimizing VLSI chip layouts.

Main Methods:

  • Developed a hybrid genetic algorithm incorporating an effective genetic search for exploration.

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  • Integrated an efficient local search method to exploit information within the search region.
  • Implemented a novel bias search strategy to balance exploration and exploitation.

    • Main Results:

    • The memetic algorithm was implemented and tested on established benchmark problems.
    • Experimental results demonstrated the MA's capability to rapidly generate optimal or near-optimal solutions.
    • The algorithm proved effective across a range of tested VLSI floorplanning scenarios.

    Conclusions:

    • The proposed memetic algorithm offers a powerful and efficient solution for VLSI floorplanning.
    • The MA effectively addresses the NP-hard nature of VLSI floorplanning.
    • This approach significantly advances VLSI design automation by improving solution quality and speed.