Feedforward neural network implementation in FPGA using layer multiplexing for effective resource utilization.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Acceleration

Background:

• Implementing large neural networks (NN) on single field-programmable gate arrays (FPGAs) is challenging due to high resource requirements, particularly numerous multipliers.
• This limitation hinders the commercial viability and cost-effectiveness of NN applications.

Purpose of the Study:

• To propose a hardware implementation strategy for multilayer feedforward neural networks (NN) on FPGAs that reduces resource requirements.
• To enable the realization of larger NNs on a single FPGA chip at a lower cost, enhancing commercial viability for online applications.

Main Methods:

• Exploiting the sequential processing of NN layers through a layer multiplexing technique.
• Implementing only the largest layer of the NN and reconfiguring it to function as different layers using a control block.
• Utilizing a control block to manage inputs, weights, biases, and excitation functions for the currently computed layer.
• Implementing multilayer networks on a Xilinx FPGA (XCV400hq240).

Main Results:

• The layer multiplexing method significantly reduces resource requirements on the FPGA.
• A moderate overhead on processing speed is observed as a trade-off for reduced resource utilization.
• Demonstrated the effectiveness of the approach for implementing large NNs on a single chip.

Conclusions:

• The proposed hardware implementation using layer multiplexing makes NN applications more commercially viable by reducing cost and improving scalability.
• This approach facilitates the deployment of NN-based solutions, such as flux estimators, for online applications.
• The method offers a practical solution for integrating complex neural networks into hardware systems efficiently.