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PLL jitter reduction by utilizing a ferroelectric capacitor as a VCO timing element.
1Microelectronics Research Laboratories, Department of Electrical and Computer Engineering, University of Colorado, Colorado Springs, CO 80933-7150, USA.
Summary
Ferroelectric capacitors offer reduced jitter in phase-locked loops (PLLs) due to their unique polarization reversal properties. This research explores ferroelectric capacitor-based PLLs as a novel approach to minimize oscillator jitter in electronic devices.
Area of Science:
- Materials Science
- Electrical Engineering
- Solid State Physics
Background:
- Ferroelectric capacitors are increasingly used in semiconductor manufacturing for memory applications.
- Their polarization reversal exhibits a nonlinear dielectric constant and hysteresis.
Purpose of the Study:
- To investigate the potential of ferroelectric capacitors in phase-locked loop (PLL) circuits.
- To explore the reduction of oscillator jitter using ferroelectric-based PLLs.
Main Methods:
- Integration of ferroelectric capacitors into semiconductor processes.
- Analysis of polarization reversal characteristics (nonlinear dielectric constant, hysteresis).
- Design and simulation of phase-locked loops utilizing ferroelectric capacitors.
Main Results:
- Ferroelectric capacitors demonstrate attributes suitable for PLLs.
- PLLs incorporating ferroelectric capacitors show promise for reduced cycle-to-cycle jitter.
- This approach represents a new avenue for oscillator jitter reduction.
Conclusions:
- Ferroelectric capacitors offer a viable path for enhancing PLL performance.
- The unique properties of ferroelectrics can be leveraged to minimize jitter in oscillators.
- Further research into ferroelectric-based PLLs is warranted for advanced memory and timing applications.
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