Faster power estimation of CMOS designs using vector compaction - a fractal approach

Area of Science:

• Electrical Engineering
• Computer Engineering
• VLSI Design

Background:

• Accurate power estimation is crucial for low-power digital complementary metal oxide semiconductor (CMOS) circuit design.
• Dynamic power estimation offers accuracy but suffers from long simulation times with large vector sets.
• Statistical methods are faster but less accurate, necessitating a balance between speed and precision.

Purpose of the Study:

• To present a novel compaction algorithm for generating compact vector sets for efficient power estimation.
• To achieve the accuracy of dynamic power estimation with the speed of statistical methods.
• To reduce the simulation time in the design cycle of integrated circuits.

Main Methods:

• Developed a compaction algorithm utilizing fractal concepts to generate representative input vector sets.
• Employed a fractal parameter to quantify correlation, enabling faster computation than explicit correlation calculation.
• Applied the algorithm to benchmark circuits from ISCAS85 and ISCAS89 suites.

Main Results:

• Achieved significant compaction ratios, with a maximum of 65.57X and an average of 38.14X.
• Maintained low power estimation errors, with a maximum of 2.4% and an average of 2.06%.
• Demonstrated a substantial reduction in simulation time due to smaller vector set sizes.

Conclusions:

• The fractal-based compaction algorithm effectively generates compact vector sets for accurate and efficient power estimation in CMOS circuits.
• This approach significantly accelerates the design cycle by reducing simulation overhead.
• The method offers a practical solution for power analysis in complex digital designs.